33 public pages mapping the NeuroEtch program from thesis to fab handoff.
This atlas turns architecture, execution, and manufacturing evidence into a coherent narrative. Recent entries now include the V26 ROM-slice closure, full-model scope gate, and package-integrity milestones.
How to read it
Why this exists
The Silicon Thesis
NeuroEtch treats a model as silicon structure rather than software loaded onto a generic accelerator.
Primary objective
Single-user latency
Reference architecture
Hard-coded inference
System objective
Latency-First Inference
The platform is organized around making one user’s token stream fast, deterministic, and cheap to serve.
Optimization target
Fast next token
Cooling posture
Air-cooled reference
Program spine
Model To Mask Flow
The project’s core loop is a translation problem: convert a model artifact into RTL, EDA runs, and eventually GDSII without losing traceability.
Major stages
Model -> RTL -> EDA -> GDS
Worker mode
Evidence-gated
Where the speed comes from
Memory Topology
The strongest architectural lever in the program is where the weights live and how often the design has to leave the die to fetch them.
Reference memory
Mask-ROM + SRAM
Infrastructure contrast
Against HBM dependence
Economic lever
Two-Mask Customization
The cost case depends on customizing a small part of the mask stack while keeping the rest of the physical platform reusable.
Customization scope
Metal/Via only
Design cycle target
~1 week
Compute primitive
MSA Architecture
The project highlights Multiply-Select-Add style dataflow as the hardware shape around frozen model structure.
Primitive
Multiply / Select / Add
Public role
Architecture pedagogy
Truth boundary
Verification Discipline
The program has explicit language for what is synthetic, what is externally run, and what is physically validated.
Evidence model
Three execution modes
Current practice
Truth policy docs
What counts as proof
Benchmark Evidence
Performance numbers only matter if the site explains where they came from and what level of confidence they deserve.
Metric focus
TPS + latency
Confidence field
High / Medium / Low
Bridge proof
TinyLlama Bridge
The TinyLlama bridge work is important because it shows the project can carry a real checkpoint into a hardware-oriented contract flow.
Milestone type
Checkpoint bridge
Program role
Parity proof
Scale gate
Qwen Feasibility Gate
The repo’s Qwen work is valuable because it makes the scaling boundary explicit: single-chip is not always viable, but partitioned execution can still be.
Feasibility output
No-go / Go
Tensor map
488 tensors
Software control plane
Runtime Platform
The webapp is not just a demo shell. It is the visible part of a control plane for runs, benchmarks, verification, and artifact tracking.
Web surface
Port 3006
Control API
Port 4201
Program tempo
Automation Loop
The repo includes discovery and autonomous-agent workflows because the project treats iteration speed as a system requirement.
Control style
Agent-assisted
Operational goal
Fast iteration
Physical path
Manufacturing Path
The manufacturing story in NeuroEtch is not abstract. The repo already encodes how OpenLane, the PDK, wrappers, and external tool adapters fit together.
EDA posture
OpenLane / OpenROAD
PDK target
Sky130 path in repo
Why it scales
Economics Of Specialization
The project’s economic thesis is that fixed-workload silicon can move both infrastructure cost and development-cycle cost in the right direction at the same time.
Reference cost
$0.0075 / 1M tokens
Rack posture
12-15 kW / rack
Last-mile honesty
Fab Handoff Discipline
The project has explicit rules for what can and cannot be claimed at the point where artifacts are prepared for fabrication.
Core rule
Evidence-backed handoff
Repo posture
Truth-policy driven
Current physical campaign
ChipFoundry Submission Path
Recent repo work shows the program operating against actual submission tooling, wrapper constraints, and remaining external blockers.
Flow target
cf init -> precheck
Current state
Green + blocked mix
Latest closure
V26 ROM-Slice Physical Closure
The April 30 run integrated a reduced Tiny-LLM ROM slice into Caravel and closed hardening with clean physical signoff checks.
ROM blocks
4 literal ROMs
Core signoff
Antenna/LVS/DRC pass
Claim control
Full-Model Weight Scope Gate
Recent tooling and audits enforce a strict boundary between reduced-slice artifacts and true full-model-weight GDS claims.
Gate output
Go / No-go
Coverage check
Tensor inventory required
External review
Share Package Evidence Chain
The latest share archive is structured for external review with checksums, manifests, and report provenance rather than raw file dumps.
Archive size
33 MB
Integrity
SHA256 + unzip check
Shared understanding
Program Baseline
Before a hardware research program can accelerate, it needs a stable internal description of what exists, what is aspirational, and what has already been proven.
Purpose
Reconciliation
Public payoff
Clearer storytelling
Forward path
Roadmap To Fab
The roadmap is not a loose wishlist. It is a sequence from model contract, to partitioning, to physical validation, to handoff discipline.
Near-term work
Partition + physical validation
Execution style
Milestone gated
ICsprout55 primitive gate
CF-1: Real Qwen Weights On Chip
CF-1 binds Qwen row 6053 as fixed on-chip INT4 ROM on an ICsprout55 tile, with RTL proof, mapped netlist, zero-DRT experimental GDS, and a machine-checkable handoff bundle. Merged to main; ECC signoff runs off-server.
Weights
1024 INT4
DRT
0 violations
ICsprout55 eight-row bundle
CF-2: Eight Qwen Rows On Chip
CF-2 scales the CF-1 primitive to eight fixed Qwen INT4 projection rows from layer-0 in_proj_qkv, with per-row RTL KAT, 16k-cell mapped netlist, and zero-DRT experimental GDS on a 280×280 µm ICsprout55 tile.
Rows
8 × 1024 INT4
Cells
16,035
ICsprout55 sixteen-row bundle
CF-3: Sixteen Qwen Rows On Chip
CF-3 doubles CF-2 coverage to sixteen fixed Qwen INT4 projection rows on a 400×400 µm ICsprout55 tile, with all-slot RTL KAT, 23k-cell mapped netlist, and zero-DRT experimental GDS.
Rows
16 × 1024 INT4
Cells
23,432
ICsprout55 dual-tensor 32+32
CF-12: Thirty-Two-Row Dual-Tensor On 700 µm
CF-12 scales CF-11 to thirty-two rows per tensor (CF-10 + CF-9): 64 RTL KAT slots, ~116k mapped cells, zero-DRT GDS on 700×700 µm.
Tensors
in_proj + out_proj
Die
700×700 µm
ICsprout55 dual-tensor layer-0
CF-11: in_proj + out_proj Dual-MAC On One Tile
CF-11 places sixteen-row CF-5 in_proj_qkv and sixteen-row CF-7 out_proj dual-MAC bundles on one 500×500 µm tile with tensor_sel mux and zero-DRT experimental GDS.
Tensors
in_proj + out_proj
MAC
32 lanes shared
ICsprout55 in_proj dual-MAC 32-row
CF-10: Dual-MAC Thirty-Two in_proj_qkv Rows On Chip
CF-10 applies dual-MAC to the full thirty-two-row in_proj_qkv bundle: 32-lane MAC, 32 cycles per dot, zero-DRT experimental GDS on 500×500 µm.
Tensor
in_proj_qkv L0
MAC
32 lanes
ICsprout55 out_proj dual-MAC 32-row
CF-9: Dual-MAC Thirty-Two out_proj Rows On Chip
CF-9 applies dual-MAC to the full thirty-two-row out_proj bundle: 32-lane MAC, 64 cycles per dot, zero-DRT experimental GDS on 500×500 µm.
Tensor
out_proj L0
MAC
32 lanes
ICsprout55 out_proj thirty-two-row
CF-8: Thirty-Two out_proj Qwen Rows On Chip
CF-8 doubles the out_proj ROM footprint to thirty-two ranked Qwen rows (2048-wide, 128 MAC cycles) on a 500×500 µm tile with zero-DRT experimental GDS.
Tensor
out_proj L0
Row width
2048 INT4
ICsprout55 out_proj dual-MAC
CF-7: Dual-MAC out_proj Qwen Rows On Chip
CF-7 keeps sixteen fixed CF-6 out_proj rows but widens the MAC to 32 lanes (dual bank fetch), halving dot-product cycles on 2048-wide rows with zero-DRT experimental GDS on 500×500 µm.
Tensor
out_proj L0
MAC
32 lanes
ICsprout55 out_proj sixteen-row
CF-6: out_proj Qwen Rows On Chip
CF-6 binds sixteen fixed Qwen INT4 rows from layer-0 out_proj (2048-wide rows, 128 MAC cycles) on a 500×500 µm ICsprout55 tile with zero-DRT experimental GDS.
Tensor
out_proj L0
Row width
2048 INT4
ICsprout55 dual-MAC sixteen-row
CF-5: Dual-MAC Qwen Rows On Chip
CF-5 keeps sixteen fixed Qwen rows but widens the MAC to 32 lanes (dual bank fetch), halving dot-product cycles on a 500×500 µm tile with zero-DRT experimental GDS.
Rows
16 × 1024 INT4
MAC
32 lanes
ICsprout55 thirty-two-row bundle
CF-4: Thirty-Two Qwen Rows On Chip
CF-4 doubles CF-3 to thirty-two fixed Qwen INT4 projection rows on a 500×500 µm ICsprout55 tile, with all-slot RTL KAT, 35k-cell mapped netlist, and zero-DRT experimental GDS.
Rows
32 × 1024 INT4
Cells
35,677