CF-7: Dual-MAC out_proj Qwen Rows On Chip

Compute scaling on the out_proj tensor chain: same weight storage as CF-6, 32-lane MAC datapath, 64 cycles per dot product. Timing closes at 75 MHz under placement RC.

Key points

Dual-port weight banks on 128-deep out_proj ROMs — no duplicated INT4 storage.

All sixteen slots pass RTL KAT with 256-bit activations over 64 cycles.

Handoff zip ready for off-server ECC.

Tensor

out_proj L0

Same sixteen rows as CF-6; dual-port bank fetch.

MAC

32 lanes

128→64 cycles per dot product versus CF-6.

Cells

~41k mapped

102,170 instances after tap/CTS/fill.

DRT

0 violations

500×500 µm die.

Timing (exp.)

75 MHz

Matches CF-5/CF-6 closing frequency.

What CF-7 proves

CF-7 combines CF-5's dual-MAC throughput trick with CF-6's out_proj tensor manifest. Mapped combinational area grows versus CF-6 (~2×) because dual lookup ports duplicate case ROM logic in synthesis.

Variant: out_proj_dual_mac_sixteen_row.

Mapped residency over 256 dual-port bank modules.

STA closes at 75 MHz (placement RC).

Honest boundaries

CF-7 is not tapeout-approved. Still sixteen rows of out_proj — not full-model on chip.

Run scripts/verify_cf7_gate.sh when tmp/ artifacts exist.

Transfer cf7_handoff_package.zip for ECC rtl2gds.