NeuroEtch research program

NeuroEtch is building model-specific AI silicon with a public evidence trail.

This frontend now tracks the current program state: V26 ROM-slice physical closure, full-model scope gates, and packaged fabrication collateral with explicit verification provenance.

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Public narrative mapped to repository milestones

Measured and target-state claims clearly separated

Admin surfaces remain protected behind authentication

NeuroEtch Stack

Model -> RTL -> GDSII

A public narrative around a hardware program that treats model structure, evidence quality, and manufacturing constraints as one system.

Focus

Latency-first inference

Lever

Two-mask specialization

Model Contract

Freeze workload assumptions

Mask-ROM Layout

Move hot weights on die

Verification

Separate target from proof

Fab Handoff

Package evidence-backed outputs

Research mode

Public thesis, private control room

01 · Reference Envelope

17k TPS

Architecture target from the HCI reference model used across project docs.

02 · Precheck Coverage

13/13

Latest local `cf precheck` run recorded all required checks passing for V26 ROM-slice wrapper.

03 · Physical Signoff

Antenna/LVS/DRC pass

Latest wrapper and macro hardening runs closed core signoff checks per changelog evidence.

04 · Share Package

33 MB zip

Curated Tiny-LLM ROM-slice handoff archive with checksums and verification reports.

Program architecture

The platform combines hardware thesis, physical flow execution, and evidence discipline.

Model-Specific Compute

Model contracts and storage decisions are treated as physical architecture choices, not runtime configuration.

Evidence-Gated Claims

Every major claim is tied to run outputs, signoff status, packaging metadata, and scope-aware documentation.

Execution Platform

Webapp, control API, runtime API, and pipeline workers provide a reproducible path from model artifact to GDS collateral.

Latest milestones

Recent repository work is now surfaced as dated, auditable milestones.

Read full technical context

2026-04-30

Evidence

V26 Tiny-LLM ROM-slice physical closure completed

Integrated four-ROM reduced Tiny-LLM slice into Caravel top RTL and regenerated wrapper/example GDS with passing hardening and smoke checks.

CHANGELOG.md

docs/research/v26_reclone_tiny_asic_execution_2026-04-27.md

2026-04-30

Evidence

Full-model scope audit and claim correction applied

Audited package scope and documented that the current archive is not full-model-weight compliant, then updated package metadata to prevent over-claims.

docs/research/v26_full_model_weight_scope_audit_2026-04-30.md

CHANGELOG.md

2026-04-30

Evidence

Hardwired full-weight tooling path added

Added generators and tests for literal INT4 ROM output and model-weight scope gating to enforce full-coverage criteria before full-model claims.

docs/research/hardwired_weight_gds_path_execution_2026-04-30.md

docs/superpowers/plans/2026-04-30-hardwired-weight-gds-path-plan.md

2026-04-30

Evidence

Share package assembled with reproducible integrity checks

Published curated ROM-slice handoff zip with manifests, SHA256 checksums, and report bundles to support external review.

CHANGELOG.md

docs/version_26_chipfoundry_handoff_archive_2026-04-24.md

Research atlas

Public pages connect architecture thesis to current V26 execution evidence.

Open Atlas

Manufacturing

ICsprout55 dual-tensor 32+32

CF-12: Thirty-Two-Row Dual-Tensor On 700 µm

CF-12 scales CF-11 to thirty-two rows per tensor (CF-10 + CF-9): 64 RTL KAT slots, ~116k mapped cells, zero-DRT GDS on 700×700 µm.

Tensors

in_proj + out_proj

Die

700×700 µm

Manufacturing

ICsprout55 dual-tensor layer-0

CF-11: in_proj + out_proj Dual-MAC On One Tile

CF-11 places sixteen-row CF-5 in_proj_qkv and sixteen-row CF-7 out_proj dual-MAC bundles on one 500×500 µm tile with tensor_sel mux and zero-DRT experimental GDS.

Tensors

in_proj + out_proj

MAC

32 lanes shared

Manufacturing

ICsprout55 in_proj dual-MAC 32-row

CF-10: Dual-MAC Thirty-Two in_proj_qkv Rows On Chip

CF-10 applies dual-MAC to the full thirty-two-row in_proj_qkv bundle: 32-lane MAC, 32 cycles per dot, zero-DRT experimental GDS on 500×500 µm.

Tensor

in_proj_qkv L0

MAC

32 lanes

Manufacturing

ICsprout55 out_proj dual-MAC 32-row

CF-9: Dual-MAC Thirty-Two out_proj Rows On Chip

CF-9 applies dual-MAC to the full thirty-two-row out_proj bundle: 32-lane MAC, 64 cycles per dot, zero-DRT experimental GDS on 500×500 µm.

Tensor

out_proj L0

MAC

32 lanes

Manufacturing

ICsprout55 out_proj thirty-two-row

CF-8: Thirty-Two out_proj Qwen Rows On Chip

CF-8 doubles the out_proj ROM footprint to thirty-two ranked Qwen rows (2048-wide, 128 MAC cycles) on a 500×500 µm tile with zero-DRT experimental GDS.

Tensor

out_proj L0

Row width

2048 INT4

Manufacturing

ICsprout55 out_proj dual-MAC

CF-7: Dual-MAC out_proj Qwen Rows On Chip

CF-7 keeps sixteen fixed CF-6 out_proj rows but widens the MAC to 32 lanes (dual bank fetch), halving dot-product cycles on 2048-wide rows with zero-DRT experimental GDS on 500×500 µm.

Tensor

out_proj L0

MAC

32 lanes

Manufacturing

ICsprout55 out_proj sixteen-row

CF-6: out_proj Qwen Rows On Chip

CF-6 binds sixteen fixed Qwen INT4 rows from layer-0 out_proj (2048-wide rows, 128 MAC cycles) on a 500×500 µm ICsprout55 tile with zero-DRT experimental GDS.

Tensor

out_proj L0

Row width

2048 INT4

Manufacturing

ICsprout55 dual-MAC sixteen-row

CF-5: Dual-MAC Qwen Rows On Chip

CF-5 keeps sixteen fixed Qwen rows but widens the MAC to 32 lanes (dual bank fetch), halving dot-product cycles on a 500×500 µm tile with zero-DRT experimental GDS.

Rows

16 × 1024 INT4

MAC

32 lanes

Manufacturing

ICsprout55 thirty-two-row bundle

CF-4: Thirty-Two Qwen Rows On Chip

CF-4 doubles CF-3 to thirty-two fixed Qwen INT4 projection rows on a 500×500 µm ICsprout55 tile, with all-slot RTL KAT, 35k-cell mapped netlist, and zero-DRT experimental GDS.

Rows

32 × 1024 INT4

Cells

35,677

Manufacturing

ICsprout55 sixteen-row bundle

CF-3: Sixteen Qwen Rows On Chip

CF-3 doubles CF-2 coverage to sixteen fixed Qwen INT4 projection rows on a 400×400 µm ICsprout55 tile, with all-slot RTL KAT, 23k-cell mapped netlist, and zero-DRT experimental GDS.

Rows

16 × 1024 INT4

Cells

23,432

Manufacturing

ICsprout55 eight-row bundle

CF-2: Eight Qwen Rows On Chip

CF-2 scales the CF-1 primitive to eight fixed Qwen INT4 projection rows from layer-0 in_proj_qkv, with per-row RTL KAT, 16k-cell mapped netlist, and zero-DRT experimental GDS on a 280×280 µm ICsprout55 tile.

Rows

8 × 1024 INT4

Cells

16,035

Manufacturing

ICsprout55 primitive gate

CF-1: Real Qwen Weights On Chip

CF-1 binds Qwen row 6053 as fixed on-chip INT4 ROM on an ICsprout55 tile, with RTL proof, mapped netlist, zero-DRT experimental GDS, and a machine-checkable handoff bundle. Merged to main; ECC signoff runs off-server.

Weights

1024 INT4

DRT

0 violations

Manufacturing

Latest closure

V26 ROM-Slice Physical Closure

The April 30 run integrated a reduced Tiny-LLM ROM slice into Caravel and closed hardening with clean physical signoff checks.

ROM blocks

4 literal ROMs

Core signoff

Antenna/LVS/DRC pass

Evidence

Claim control

Full-Model Weight Scope Gate

Recent tooling and audits enforce a strict boundary between reduced-slice artifacts and true full-model-weight GDS claims.

Gate output

Go / No-go

Coverage check

Tensor inventory required

Execution

External review

Share Package Evidence Chain

The latest share archive is structured for external review with checksums, manifests, and report provenance rather than raw file dumps.

Archive size

33 MB

Integrity

SHA256 + unzip check

Execution

Program spine

Model To Mask Flow

The project’s core loop is a translation problem: convert a model artifact into RTL, EDA runs, and eventually GDSII without losing traceability.

Major stages

Model -> RTL -> EDA -> GDS

Worker mode

Evidence-gated

Evidence

Truth boundary

Verification Discipline

The program has explicit language for what is synthetic, what is externally run, and what is physically validated.

Evidence model

Three execution modes

Current practice

Truth policy docs

Execution

Forward path

Roadmap To Fab

The roadmap is not a loose wishlist. It is a sequence from model contract, to partitioning, to physical validation, to handoff discipline.

Near-term work

Partition + physical validation

Execution style

Milestone gated

Program sequence

Milestone progression from contract scope to fabrication package.

01 · ICsprout Primitive

CF-1 places a real Qwen INT4 row as fixed on-chip ROM with ICsprout55 mapped GDS evidence.

OpenROAD tap/CTS/repair/route, zero DRT, handoff manifest, 90 MHz recommended timing under placement RC.

02 · Contract + Scope

The project now separates reduced-slice demos from full-model claims using explicit scope gates.

Full-model-weight path work introduced contract checks to prevent over-claiming tapeout status.

03 · Hardwired Path

INT4 hardwired ROM generation is now scripted from model-slice artifacts.

Bundle tooling emits per-tensor ROMs, manifests, and image hashes for deterministic reproduction.

04 · Physical Closure

V26 ROM-slice integrated into Caravel user project and closed through hardening checks.

Antenna, LVS, DRC, KLayout loading, cocotb smoke, and local precheck evidence are all captured.

05 · Package Discipline

Handoff archives now ship with manifest, checksums, and explicit model-scope labeling.

Packaging notes distinguish reduced-slice artifacts from any full-model-weight fabrication claim.

06 · Platform Exposure

The frontend can now communicate real run outcomes, not only the static thesis.

Public narrative is aligned to recent evidence from changelog and research notes.

Current posture

Proof-backed, scope-aware communication.

Reduced-slice vs full-model boundaries are explicit.

Package integrity and report provenance are documented.

Physical checks are surfaced with run-level context.

Public + admin split

Open research narrative, protected operator control room.

Public visitors see thesis, milestones, and evidence references. Internal users keep access to run orchestration, control endpoints, and operational diagnostics.

Research pages Admin login Admin dashboard