CF-9: Dual-MAC Thirty-Two out_proj Rows On Chip

Throughput scaling on the out_proj chain: same 32 rows as CF-8, half the cycles via dual bank fetch. STA closes at 75 MHz.

Key points

512 dual-port bank modules with five-bit row mux.

All thirty-two slots pass RTL KAT with 256-bit activations.

Largest experimental primitive gate so far on this server.

Tensor

out_proj L0

Same 32 rows as CF-8; dual-port fetch.

MAC

32 lanes

128→64 cycles per dot versus CF-8.

Cells

~61k mapped

142,809 instances after tap/CTS/fill.

DRT

0 violations

500×500 µm die.

Timing (exp.)

75 MHz

Matches CF-7 closing frequency.

What CF-9 proves

CF-9 closes the out_proj scaling ladder: sixteen-row single-MAC (CF-6), sixteen-row dual-MAC (CF-7), thirty-two-row single-MAC (CF-8), and thirty-two-row dual-MAC — all with machine-checkable proofs.

Variant: out_proj_dual_mac_thirty_two_row.

Mapped residency over 512 dual-port bank modules.

STA closes at 75 MHz under placement RC.

Honest boundaries

Still thirty-two rows of one projection tensor — not full-model on chip.

Run scripts/verify_cf9_gate.sh when tmp/ artifacts exist.

Transfer cf9_handoff_package.zip for ECC rtl2gds.