NeuroEtch
Loading
ICsprout55 dual-MAC sixteen-row
Compute scaling without ROM scaling: same weight storage as CF-3, 32-lane MAC datapath, 32 cycles per dot product. Timing closes at 75 MHz under placement RC.
Key points
Rows
16 × 1024 INT4
Same bundle as CF-3; dual-port bank fetch.
MAC
32 lanes
64→32 cycles per dot product versus CF-3.
Cells
~46k mapped
112,305 instances after tap/CTS/fill.
DRT
0 violations
500×500 µm die (400 µm failed placement).
Timing (exp.)
75 MHz
Matches CF-3 closing despite wider MAC.
CF-5 shows throughput can scale via wider MAC logic while reusing the same sixteen-row ROM footprint as CF-3. Mapped combinational area grows (~2×) because dual lookup ports duplicate case ROM logic in synthesis.
CF-5 is not tapeout-approved. Still sixteen rows of in_proj_qkv — not full-model on chip.