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ICsprout55 thirty-two-row bundle
Largest row-mux ROM milestone: thirty-two pinned rows selectable via row_index[4:0]. Timing closes at 70 MHz under placement RC on the larger die.
Key points
Rows
32 × 1024 INT4
Includes all sixteen CF-3 rows plus next sixteen by activity rank.
Cells
35,677
Mapped netlist; 91,021 instances after tap/CTS/fill.
DRT
0 violations
First-route pass on 500×500 µm die.
GDS SHA-256
03b36c8d…
Pinned in designs/cf4/manifests/cf4_physical_artifacts.json.
Timing (exp.)
70 MHz
100 MHz WNS −3.81 ns; ROM scale continues to tighten margin.
CF-4 shows the row-mux ROM pattern scales to thirty-two independently verifiable Qwen rows while staying inside the model_primitive claim boundary. Die area grows to 500×500 µm; timing margin tightens to 70 MHz.
CF-4 is not tapeout-approved. Do not extrapolate 75–90 MHz from smaller CF tiles—the thirty-two-row bundle closes at 70 MHz under placement RC on this server.