CF-1: Real Qwen Weights On Chip

This is an honest model_primitive milestone on main: one projection row on silicon-class collateral, not a full-model or fab-ready claim. OpenROAD tap/CTS/repair/route, pinned checksums, 90 MHz recommended timing, and portable handoff zip for ECC rtl2gds on a signoff host.

Key points

Real model tensor bytes are pinned, byte-verified, and fixed in generated RTL.

Mapped ICsprout55 netlist and residency proofs pass with ECC dont_use policy.

Experimental GDS is packaged for off-server ECC/signoff; foundry DRC/LVS not run here.

Weights

1024 INT4

Qwen in_proj_qkv row 6053 as literal ROM.

DRT

0 violations

OpenROAD detailed route on repaired hardened DEF.

GDS SHA-256

c74619a6…

Pinned in designs/cf1/manifests/cf1_physical_artifacts.json.

Timing (exp.)

90 MHz

Canonical handoff; repair_timing alt closes ~97 MHz (not promoted).

What CF-1 proves

CF-1 demonstrates that NeuroEtch can take a real Qwen weight row, store it as on-chip logic, simulate the compute tile against a software golden model, and map the design into ICsprout55 standard cells with a documented physical flow.

RTL known-answer proof against row 6053.

9013-cell mapped netlist with weight-bank residency proof.

19,592-instance hardened layout with tapcells, CTS, and fillers.

Honest boundaries

CF-1 is not tapeout-approved. ECC rtl2gds and foundry signoff decks were unavailable on the build server. Timing at 100 MHz is not closed under the experimental RC model.

Use cf1_clk_recommended.sdc (90 MHz) for honest operating claims.

Run scripts/verify_cf1_gate.sh locally for full gate checks.

Transfer cf1_handoff_package.zip and follow docs/how_to/cf1_ecc_signoff_off_server.md.