V26 ROM-Slice Physical Closure

This milestone is important because it moved the project from planning language into an artifact-complete closure package for a concrete design slice. The outcome is limited in scope, but it is physically grounded and reproducible.

Key points

This is a physical closure of a reduced model slice, not a full-model tapeout claim.

The result includes regenerated `user_proj_example` and `user_project_wrapper` GDS assets.

Verification evidence spans cocotb smoke, KLayout load checks, and precheck reports.

ROM blocks

4 literal ROMs

Reduced Tiny-LLM INT4 slice integrated into top RTL.

Core signoff

Antenna/LVS/DRC pass

Macro and wrapper hardening runs both closed required signoff checks.

Precheck

13/13 required pass

Latest local ChipFoundry precheck passed all required checks.

What was integrated

The V26 update wired generated ROM-slice artifacts into Caravel top RTL and aligned GPIO/OEB definitions with actual macro IO direction before re-hardening.

That integration step matters because it keeps generated model artifacts tied to concrete wrapper behavior rather than staying as isolated files.

Why this matters publicly

A credible hardware narrative needs proof objects, not only architectural claims. This closure gives the public site a concrete, dated milestone with reproducible package outputs.

Hardening and signoff reports are attached to named run tags.

GDS load checks are explicitly recorded.

Scope is stated as reduced slice to avoid misleading interpretation.