Memory Topology

Repo material repeatedly emphasizes on-chip Mask-ROM and SRAM as the differentiator against off-chip-memory-heavy systems. NeuroEtch studies that same topology because it changes latency, energy, and system density at once.

Key points

Memory is not a supporting detail here; it is the thesis.

The architecture works only if data placement is frozen as aggressively as compute structure.

The public research story should make memory visible rather than burying it in the spec sheet.

Reference memory

Mask-ROM + SRAM

The repo uses this as the core HCI memory signature.

Infrastructure contrast

Against HBM dependence

The comparison tables stress this difference.

System effect

Lower movement

Performance comes from reducing distance and indirection.

On-chip persistence as a system decision

When model weights are carried on the chip rather than streamed from an external memory hierarchy, the control path simplifies and the latency budget compresses.

That design choice is also what makes the architecture less flexible. Weight storage becomes a physical asset, not just a runtime input.

What NeuroEtch learns from this

The project uses the memory story to organize its own research questions around partitioning, checkpoint bridges, storage encoding, and verification discipline.

Which weights can be structurally frozen?

Which state must remain mutable in SRAM or external systems?

How do those choices interact with partition count and die area?